Edge-triggered latches have commonly been used in electronic systems for sampling externally generated signals. In most applications, such signals would arrive asynchronously with respect to the system clock which controls a system's internal operations. A signal input is usually sampled with the edge of the system clock which triggers a latch to register the state of the signal. Ideally, the input signal should be sampled only when it is in either one of two bistable states, each representing a binary value. Unfortunately, there often exists a high probability that, at any sampling instant, the signal level is at the metastable state of the latch, i.e. at a level where the state is indeterminable.
To lower the probabilty of metastability, conventional edge-triggered latches are required to have a setup time, which is the minimum duration in which the input signal has been settled in one of the bistable states before the occurrence of the sampling pulse. When high speed signal processing is required, however, an edge-triggered latch having low setup time and decreased metastability problem is desired.
U.S. Pat. No. 4,227,699 discloses a latch circuit operable as a D-type edge trigger which is basically formed by combining two polarity latches with other logic circuits. Although the latch can conform to LSSD design rules, it nevertheless suffers from long setup time and metastability problem.
It is an object of this invention to provide apparatus and method for reducing the setup time of an edge-triggered latch.
It is also an object of this invention to provide apparatus and method for eliminating a metastability problem in an edge-triggered latch.